`timescale 1 ns/ 1 ns
module hdmi_tb();


// test vector input registers
reg sys_clk;
reg adc_clk;
reg sys_rst_n;
// wires      
reg [0:0] Write_Enable;
reg [9:0] Write_Address;
reg [9:0] Read_Address;
reg [7:0] Write_Data;
wire [7:0] Read_Data;
reg [0:0] Read_Enable;

// assign statements (if any)                       
blk_mem_gen_0 u_blk_mem_gen_0(
    .addra(Write_Address),
    .clka(sys_clk),
    .dina(Write_Data),
    .wea(Write_Enable),
    
    .addrb(Read_Address),
    .clkb(sys_clk),
    .doutb(Read_Data),
    .enb(Read_Enable)
);
    
initial
begin
    sys_clk<=1'b0;
    sys_rst_n<=1'b1;
    Write_Data <=2'b10;
    Write_Address <=1'b1; 
    Read_Address <=1'b1; 
    #100
    sys_rst_n<=1'b0;
    Read_Enable<=1'b1;
    Write_Enable<=1'b1;
    #2000000
    $stop;
end

always
begin                                                  
    #8 sys_clk=~sys_clk;  
    Write_Data <= Write_Data + 2'b10;
    Write_Address <= Write_Address+1'b1; 
    Read_Address <= Read_Address+1'b1; 
    #8 sys_clk=~sys_clk;  
end 
                                              
endmodule

